This invention relates to semiconductor memory devices, and more particularly to a dynamic memory device having a refresh mode.
Battery-operated computers are constructed with circuitry tailored for reducing the standby power required. The DRAMs used to construct the main memory are a significant part of the circuitry of a laptop computer or the like, and so are a target for power reduction in the standby mode. A memory that is non-volatile is a necessity, so that data can be preserved during idle periods. If this non-volatile memory can be constructed using DRAMs the parts cost is greatly reduced, so DRAMs with battery back-up are utilized. The requirement for refresh is the main problem is using DRAMs in this manner. A DRAM must be periodically refreshed to avoid deterioration of stored data. Various standby modes for DRAMs have been proposed, and parts are manufactured using some of these concepts. For example, DRAMs are produced having battery backup modes using very low current, but requiring unconventional sequencing of the address strobes, and lengthy recovery periods when exiting the backup mode, before normal read or write cycles can be executed. Other such products achieve low standby current, but require the system to cycle the address strobe, which more than offsets the current savings in the component.
In prior approaches, therefore, the goal of low standby current drain has been achieved at the expense of either a long recovery period before normal operation can be resumed, or an increase in the system power requirements, offsetting the power savings in the DRAMs devices.
It is the principal object of this invention to provide an improved low-power standby mode of operation of dynamic memory device. Another object is to provide a low-power mode of operation of a dynamic memory in which the device recovers from this mode quickly and read and write operations can be performed without delay. A further object is to provide a low-power mode of operation of a memory device without increasing the power drain on other parts of the system due to signals needed to maintain the memory device in the standby mode.